1. Field of the Invention
This invention relates generally to a semiconductor fabrication process, and, more particularly, to controlling cumulative wafer effects in the semiconductor fabrication process.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in continual improvements in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
During the fabrication process, various events may take place that affect the performance of the devices being fabricated. That is, variations in the fabrication process result in device performance variations. Factors, such as feature critical dimensions, doping levels, contact resistance, particle contamination, etc., may potentially affect the end performance of the device. Various tools in the processing line are controlled, in accordance with performance models, to reduce processing variation. Commonly controlled tools include photolithography steppers, polishing tools, etching tools, and deposition tools. Pre-processing and/or post-processing metrology data is supplied to process controllers for the tools. Operating recipe parameters, such as processing time, are calculated by the process controllers based on the performance model and the metrology information to attempt to achieve post-processing results as close to a target value as possible. Reducing variation in this manner leads to increased throughput, reduced cost, higher device performance, etc., which equates to increased profitability.
Semiconductor manufacturing processes, which have become increasingly more reliable and robust, may include a plurality of processing tools that cooperate with each other to process semiconductor devices, such as microprocessors, memory devices, ASICs, etc. Typically, workpieces, such as semiconductor wafers, are exposed to a sequence of processes within the manufacturing process, where the sequence of processes may have some cumulative effect on the wafers, as the wafers progress from one processing tool to another. One example of a cumulative effect is oxide loss that occurs over the process life cycle of the wafer. That is, wafers having an oxide layer deposited initially therein may experience oxide loss caused by the different processes, such as etching, cleaning, and the like, as the wafers proceed through the manufacturing system 100. Similarly, other types of cumulative effects may also occur throughout the process life cycle of a wafer. These cumulative effects, if excessive, however, can sometimes have a deleterious effect on the overall process, as wastage of wafers may occur because of misprocessing.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.